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Altera_Forum's avatar
Altera_Forum
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10 years ago

use verilog module in vhdl and the test bench

I am trying to instantiating a verilog module in a vhdl design. There is no error shown after compile it but i can't get the corresponding result in the modelsim. Does anyone can help me to che...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Thank you for your reply! I didn't realize the reset is active low, thank you so much!

However, I have another question about the I2C.v, I know I shouldn't ask it in here...

Why I2C_SDAT is in high impedance if SDO is '1'? Is that means I2C_SDAT can't transmit the data? 

wire I2C_SDAT = SDO?1'bz:0 ;

I search it on google already and there is the same question but I still don't understand...

http://www.alteraforum.com/forum/showthread.php?t=20018 (http://www.alteraforum.com/forum/showthread.php?t=20018)