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BDarji's avatar
BDarji
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Usage of negative edge trigger for dual clock RAM

Dear all, Greetings of the Day! We are having one dual port RAM with separate clock for port A and Port B. Port B related signals are driven within FPGA. While port A related signals will be driven...
Hdl
Timing
_AK6DN_'s avatar
_AK6DN_
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Since the signals for port A are derived from an external source, why just not add an inversion to
flip the (external) negative clock edge to an (internal) positive clock edge? The signals have to go
thru I/O drivers and logic to get on chip anyway, so it will cost you effectively nothing, and make
the design much more straightforward, a standard posedge referenced ram block on both ports.

  • BDarji's avatar
    BDarji
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hello,

    Thank you for answer.

    Let me try to give more information.

    In above image, external DSP is driving chip select, write request, address and data. Based on those signals, we should perform memory write operation. I have also shown some internal signals which we are planning to derive from above and then pass it to memory.

    As DSP is driving signals out on negative edge of clock, I thought it would be good to use negative edge itself.

    You mentioned that clock should be inverted. If we invert clock, will not it effect timings?

    Please let me know if my understanding is wrong.

    Have a Nice Day!

    Regards,

    Bhaumik