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Altera_Forum's avatar
Altera_Forum
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16 years ago

unsigned decimal to binary conversion in verilog

Dear all,

I have some problem with the implementation of unsigned decimal to binary conversion. I need this conversion for my 32-bits fast adder design.

Could anybody tell me how to hold an unsigned decimal value in verilog? my algorithm for the code is as below:

module converter(A, B, CLK);

input A;

input CLK;

output [3:0] B;

real j = 12;

reg [3:0] quotient;

integer count;

reg [3:0] z;

always@(posedge CLK)

if(A)

for(count=0; count < 4; count = count + 1)

begin

quotient[count] <= j / 2;

z[count] <= j % 2;

j <= quotient[count];

B[count] = z[count];

if(j < 2)

begin

count = 3;

end

end

endmodule

The code above is trying to convert an unsigned decimal of 12 into its binary representation, which is 1100, hold by the register B[3:0] and serve as output port as well.

So could anybody help to give me some idea on how i solve this issue? Thanks in advance

Regards,

Robbie

9 Replies

  • ak6dn's avatar
    ak6dn
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    FYI you are responding to a thread where the last post was 11 years ago ...

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    The question sounds confused. All numbers (signed, unsigned) have basically a binary representation in digital processing. There's nothing to convert.

    Real is however an abstract data type for simulation purposes only. It's not synthesizable. Special binary formats exist for floating point numbers (e.g. IEEE single and double), but the present code is dealing with integer numbers only and doesn't need float.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    The problem is i wan to have an user friendly interface, which allow user to enter decimal numbers directly from hardware input and allow my code to basically intepret it into binary representation.

    The question is how do I able to represent my decimal number in verilog?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    The term "decimal" has no exact meaning.

    Is your input format a binary coded decimal (commonly referred as BCD, a representation in which each decimal digit represented by four bits) or something else?

    In the former case, search the Web for BCD to binary conversion. You are supposed to find a lot of examples.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I'm not into converting BCD into binary representation. Instead, I wan to provide a user friendly hardware input using DE2 board, where I only need to key in decimal numbers for my 32-bits fast adder design.

    I also try to do some logical shift to my decimal numbers, but it seems to shift binary position instead of decimal places. Anyone have better idea on how to do this?

    Thanks

    Regards

    Robbie
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    But what you describe sounds much like BCD coded input in my ears. You may want to clarify, what your "user friendly hardware input" looks like. If you possibly refer to the DE2 toggle switches, you should specify the intended switch coding.

    Shifting by decimal places in a binary number system means multiplying or dividing numbers by a factor of 10. Early electronic pocket calculators have been somethings using decimal arithmetic (as mechanical calculators did before), but these days are long gone.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I think that the goal it's to run the code in a simulation enviroment, and test it

    Decimal unsigned are option from Quartus to set or see an input or output

    Indeed we are talking of integer subtype value like natural or positive as the code says.

    Similar problem are bit_vector to natural conversion
  • the_prodigal_son's avatar
    the_prodigal_son
    Icon for New Contributor rankNew Contributor
    4 years ago

    Below code is hardcoded for 8 bits. Fine tuning and optimization can be done. But this does the job.

    Hope this helps

    RTL :

    module dec_bin

    #(parameter no_of_bits = 8,

    parameter binary = 2)(

    output reg [(no_of_bits/2) - 1 : 0] counter,

    output reg [no_of_bits - 1 : 0] bin,

    input reset, clk,

    input [7:0] in

    );

    reg [no_of_bits - 1 : 0] r0;

    reg [no_of_bits - 1 : 0] r1;

    reg [no_of_bits - 1 : 0] r2;

    reg [no_of_bits - 1 : 0] r3;

    reg [no_of_bits - 1 : 0] r4;

    reg [no_of_bits - 1 : 0] r5;

    reg [no_of_bits - 1 : 0] r6;

    reg [no_of_bits - 1 : 0] r7;

    reg bin0 = 1'b0;

    reg bin1 = 1'b0;

    reg bin2 = 1'b0;

    reg bin3 = 1'b0;

    reg bin4 = 1'b0;

    reg bin5 = 1'b0;

    reg bin6 = 1'b0;

    reg bin7 = 1'b0;

    initial

    begin

    counter = 4'b0000;

    bin = 8'b0000_0000;

    r0 = 8'b0000_0000;

    r1 = 8'b0000_0000;

    r2 = 8'b0000_0000;

    r3 = 8'b0000_0000;

    r4 = 8'b0000_0000;

    r5 = 8'b0000_0000;

    r6 = 8'b0000_0000;

    r7 = 8'b0000_0000;

    end

    always @ (posedge clk)

    begin

    if (reset)

    begin

    counter <= 4'b0000;

    bin <= 8'b0000_0000;

    end

    else

    begin

    counter <= counter + 4'b0001;

    r0 <= in / binary;

    r1 <= r0 / binary;

    r2 <= r1 / binary;

    r3 <= r2 / binary;

    r4 <= r3 / binary;

    r5 <= r4 / binary;

    r6 <= r5 / binary;

    r7 <= r6 / binary;

    bin0 = ((r0 * binary) == in) ? 1'b0 : 1'b1;

    bin1 = ((r1 * binary) == r0) ? 1'b0 : 1'b1;

    bin2 = ((r2 * binary) == r1) ? 1'b0 : 1'b1;

    bin3 = ((r3 * binary) == r2) ? 1'b0 : 1'b1;

    bin4 = ((r4 * binary) == r3) ? 1'b0 : 1'b1;

    bin5 = ((r5 * binary) == r4) ? 1'b0 : 1'b1;

    bin6 = ((r6 * binary) == r5) ? 1'b0 : 1'b1;

    bin7 = ((r7 * binary) == r6) ? 1'b0 : 1'b1;

    bin = {bin7, bin6, bin5, bin4, bin3, bin2, bin1, bin0};

    $display($time," The value of counter is %b%b%b%b%b%b%b%b %d", bin7, bin6, bin5, bin4, bin3, bin2, bin1, bin0, counter);

    end

    end

    endmodule

    Testbench :

    module dec_bin_tb

    #(parameter no_of_bits = 8,

    parameter time_period = 20)(

    );

    wire [(no_of_bits/2) - 1 :0] COUNTER;

    wire [(no_of_bits) - 1 : 0] BIN;

    reg CLK, RESET;

    reg [7:0] IN;

    dec_bin db1 (.counter(COUNTER), .bin(BIN), .clk(CLK), .reset(RESET), .in(IN));

    initial

    begin

    CLK = 1'b0;

    RESET = 1'b0;

    #time_period RESET = 1'b1;

    IN = 50;

    #time_period RESET = 1'b0;

    #580 RESET = 1'b1;

    #time_period RESET = 1'b0;

    end

    always

    #time_period CLK = ~CLK;

    endmodule