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Altera_Forum
Honored Contributor
Honored Contributorunsigned decimal to binary conversion in verilog
Dear all, I have some problem with the implementation of unsigned decimal to binary conversion. I need this conversion for my 32-bits fast adder design. Could anybody tell me how to hold...
Altera_ForumHonored Contributor
Honored ContributorI think that the goal it's to run the code in a simulation enviroment, and test it
Decimal unsigned are option from Quartus to set or see an input or output Indeed we are talking of integer subtype value like natural or positive as the code says. Similar problem are bit_vector to natural conversion
