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Altera_Forum's avatar
Altera_Forum
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15 years ago

"unsigned" changes to "std_logic_vector" when creating hdl from current bdf

hi there,

When i do a "create hdl from current design file" the vhdl output that is generated has all entity "UNSIGNED" declarations swapped for "STD_LOGIC_VECTOR". Also the "USE IEEE.NUMERIC_STD.ALL" statement is not copied/generated into the vhdl file, while i declare it in the primitive entities.

It's starting to irritate me that i have to keep replacing all the declerations every time i change the primitive entities.

And while i'm at it, is there a way to do a bottom up build. Right now every time i change a primitive i have to create the symbol file for the entity, update the block of that entity in a block schematic, do a "create hdl from current design file", make a symbol of that, and then update that block in the top block schemtic and then rebuild. can i make that happen with one click?

thanks,

Wernher

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    The bdf to HDL (and vice versa) option is very basic, and will only use std_logic_vector. The only way for it to keep your package usages is to do everything in VHDL without any graphical files.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    The bdf to HDL (and vice versa) option is very basic, and will only use std_logic_vector. The only way for it to keep your package usages is to do everything in VHDL without any graphical files.

    --- Quote End ---

    thanks, i guess i'm going to have to brush up on the vhdl components.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Components are very simply, it is simply the entity declaration copied and entity replaced with component.

    But theres no need for components, you can just use direct instantiation. Its much safer as you dont have to keep two copies of the same thing. like this 

    
----------------------------------
--My_lib is the library - this will usually be work
--(arch) is optional, it allows you to select which architecture you want to use
--If there is only one architecture, it uses that one
------------------------------------
my_inst : entity my_lib.my_entity(arch)
generic map (
...
)
port map (
);