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Altera_Forum
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15 years ago

"unsigned" changes to "std_logic_vector" when creating hdl from current bdf

hi there, When i do a "create hdl from current design file" the vhdl output that is generated has all entity "UNSIGNED" declarations swapped for "STD_LOGIC_VECTOR". Also the "USE IEEE.NUMERIC_S...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Components are very simply, it is simply the entity declaration copied and entity replaced with component.

But theres no need for components, you can just use direct instantiation. Its much safer as you dont have to keep two copies of the same thing. like this 


----------------------------------
--My_lib is the library - this will usually be work
--(arch) is optional, it allows you to select which architecture you want to use
--If there is only one architecture, it uses that one
------------------------------------
my_inst : entity my_lib.my_entity(arch)
generic map (
...
)
port map (
);