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Altera_Forum
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15 years ago

"unsigned" changes to "std_logic_vector" when creating hdl from current bdf

hi there, When i do a "create hdl from current design file" the vhdl output that is generated has all entity "UNSIGNED" declarations swapped for "STD_LOGIC_VECTOR". Also the "USE IEEE.NUMERIC_S...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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The bdf to HDL (and vice versa) option is very basic, and will only use std_logic_vector. The only way for it to keep your package usages is to do everything in VHDL without any graphical files.

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thanks, i guess i'm going to have to brush up on the vhdl components.