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tsoundi's avatar
tsoundi
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2 years ago
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Unrecognized output fir II

Hi,

I made a fir filter using the FIR II in the ip catalog of Quartus Prime Lite Edition.

When implementing my fir filter I get an Unrecognized signal at the output of the filter.

I made a testbench for the fir filter where I send a random value to see if I get something at the output I just want to have something at the output instead of "Unrecognized" from there I can further work on my application. I put a screenshot of the waveform and I put the testbench code as attachment.

What am I doing wrong. I am a student that started not a long time ago to work with VHDL and Quartus so I am not really experimented.

Thank you very much,

Daoud

  • Kshitij_Intel's avatar
    Kshitij_Intel
    2 years ago

    Hi,


    When you are using the FIR II IP with Lite edition there will be time limited SOF will generate.


    Are you giving any reset to the FIR IP? If Yes, try changing the reset polarity on HW(eg. active low to active high).


    Thank you

    Kshitij Goel


8 Replies

  • Kshitij_Intel's avatar
    Kshitij_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,


    Can you please try giving the input data from NCO IP and test it.


    Thank you

    Kshitij Goel


  • Kshitij_Intel's avatar
    Kshitij_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,


    Please provide initial reset to the FIR II IP for some clock cycles.


    Thank you

    Kshitij Goel


    • tsoundi's avatar
      tsoundi
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hello K**bleep**ij Goel,

      I managed to make the fir filter work meanwhile so I am not having an issue anymore. It was a problem with the sink valid pulse that was not initialized correctly.

      The issue now is when I try to implement my code on the FPGA itself I don't get any output at all. The testbench works perfectly and all but when loading the FPGA I get zero's at my output. Is it possible that the fir compiler does not work when not having a license I am working on a free version of Quartus prime so maybe that is the issue ?

      Thank you,

      Daoud

  • Kshitij_Intel's avatar
    Kshitij_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Daoud,


    Do you mean you are using Lite edition? FIR II IP will work but it will need license to generate full bitstream, else it will be time-limited bitstream. If you are able to generate the SOF then it should work on HW.


    How are you trying to see the output data? Are you trying to capture using STP?


    Thank you

    Kshitij Goel


    • tsoundi's avatar
      tsoundi
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hi,

      Yes, I am using Quartus Prime Lite edition. I am utilizing the Nuand bladeRF with a Cyclone V FPGA. You can find instructions on how to build the project and deploy it on the board in this GitHub repository: https://github.com/Nuand/bladeRF/wiki/FPGA-Development. I am executing specific Linux commands to build the project, which generates an ".rbf" file containing the bitstream. Afterwards, I load this file onto the FPGA.

      To observe the output, I have SMA connections on the bladeRF which receives and send data with antennas, as shown in the picture below. I connect the bladeRF to my computer and utilize the GNU Radio software to view the output. I have successfully implemented numerous codes without the FIR II filter, where the output is clearly visible. However, when I incorporate the FIR filter, I am unable to observe any output.

      Thank you,

      Daoud

  • Kshitij_Intel's avatar
    Kshitij_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,


    When you are using the FIR II IP with Lite edition there will be time limited SOF will generate.


    Are you giving any reset to the FIR IP? If Yes, try changing the reset polarity on HW(eg. active low to active high).


    Thank you

    Kshitij Goel


    • tsoundi's avatar
      tsoundi
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hi,

      Thank you very much I overlooked this detail. I did it correctly in my testbench but did not invert the reset in the project.

      I changed this and I get an output now !

      greetings,

      Daoud

  • Kshitij_Intel's avatar
    Kshitij_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,


    As we do not receive any response from you on the previous reply that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    Thank you

    Kshitij Goel