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tsoundi's avatar
tsoundi
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Unrecognized output fir II

Hi, I made a fir filter using the FIR II in the ip catalog of Quartus Prime Lite Edition. When implementing my fir filter I get an Unrecognized signal at the output of the filter. I made a testbe...
Simulation
  • Kshitij_Intel's avatar
    Kshitij_Intel
    3 years ago

    Hi,


    When you are using the FIR II IP with Lite edition there will be time limited SOF will generate.


    Are you giving any reset to the FIR IP? If Yes, try changing the reset polarity on HW(eg. active low to active high).


    Thank you

    Kshitij Goel


Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi,


Please provide initial reset to the FIR II IP for some clock cycles.


Thank you

Kshitij Goel


  • tsoundi's avatar
    tsoundi
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hello K**bleep**ij Goel,

    I managed to make the fir filter work meanwhile so I am not having an issue anymore. It was a problem with the sink valid pulse that was not initialized correctly.

    The issue now is when I try to implement my code on the FPGA itself I don't get any output at all. The testbench works perfectly and all but when loading the FPGA I get zero's at my output. Is it possible that the fir compiler does not work when not having a license I am working on a free version of Quartus prime so maybe that is the issue ?

    Thank you,

    Daoud