New ContributorUniversity VWF won't work
This is not a liscence issue and I've run it in admin mode to no avail. University VWF file won't analyze logic. Won't even give me a reason for the error. I noticed that the path for the last file it's trying to use is obviously invalid as it implies a folder with no name in the specified path. I've also messed with the simulation eda tool settings with no luck. This error happens the same way in Logic and Timing analysis. This is for 21.1 Quartus Prime Lite Edition.
Determining the location of the ModelSim executable...
Using: c:/intelfpga_lite/21.1/questa_fse/win64/
To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both Questa Intel FPGA Edition and ModelSim executables are available, Questa Intel FPGA Edition will be used.
**** Generating the ModelSim Testbench ****
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off ClockProject -c ClockProject --vector_source="C:/intelFPGA_lite/21.1/quartus/bin64/Waveform.vwf" --testbench_file="C:/intelFPGA_lite/21.1/quartus/bin64/simulation/qsim/Waveform.vwf.vt"
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition
Info: Copyright (C) 2022 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Tue Jan 17 19:41:05 2023
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off ClockProject -c ClockProject --vector_source=C:/intelFPGA_lite/21.1/quartus/bin64/Waveform.vwf --testbench_file=C:/intelFPGA_lite/21.1/quartus/bin64/simulation/qsim/Waveform.vwf.vt
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Completed successfully.
Completed successfully.
**** Generating the functional simulation netlist ****
quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/intelFPGA_lite/21.1/quartus/bin64/simulation/qsim/" ClockProject -c ClockProject
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition
Info: Copyright (C) 2022 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Tue Jan 17 19:41:07 2023
Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=C:/intelFPGA_lite/21.1/quartus/bin64/simulation/qsim/ ClockProject -c ClockProject
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file ClockProject.vo in folder "C:/intelFPGA_lite/21.1/quartus/bin64/simulation/qsim//" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4727 megabytes
Info: Processing ended: Tue Jan 17 19:41:08 2023
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Completed successfully.
**** Generating the ModelSim .do script ****
C:/intelFPGA_lite/21.1/quartus/bin64/simulation/qsim/ClockProject.do generated.
Completed successfully.
**** Running the ModelSim simulation ****
c:/intelfpga_lite/21.1/questa_fse/win64//vsim -c -do ClockProject.do
Error.
