engtjm
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Re: University VWF won't work
Hi Richard, I have tried to run the functional simulation in the University Program VWF, and I get the same error. Please see below. With best regards, Tim Determining the location of the ModelSim executable... Using: C:/intelFPGA_lite/21.1/questa_fse/win64 To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both Questa Intel FPGA Edition and ModelSim executables are available, Questa Intel FPGA Edition will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder2 -c decoder2 --vector_source="C:/Users/engtj/Quartus/decoder2/Waveform.vwf" --testbench_file="C:/Users/engtj/Quartus/decoder2/simulation/qsim/Waveform.vwf.vt" Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition Info: Copyright (C) 2022 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Fri Jan 27 16:38:15 2023 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder2 -c decoder2 --vector_source=C:/Users/engtj/Quartus/decoder2/Waveform.vwf --testbench_file=C:/Users/engtj/Quartus/decoder2/simulation/qsim/Waveform.vwf.vt Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Completed successfully. Completed successfully. **** Generating the functional simulation netlist **** quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/engtj/Quartus/decoder2/simulation/qsim/" decoder2 -c decoder2 Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition Info: Copyright (C) 2022 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Fri Jan 27 16:38:17 2023 Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=C:/Users/engtj/Quartus/decoder2/simulation/qsim/ decoder2 -c decoder2 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file decoder2.vo in folder "C:/Users/engtj/Quartus/decoder2/simulation/qsim//" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 4649 megabytes Info: Processing ended: Fri Jan 27 16:38:17 2023 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:01 Completed successfully. **** Generating the ModelSim .do script **** C:/Users/engtj/Quartus/decoder2/simulation/qsim/decoder2.do generated. Completed successfully. **** Running the ModelSim simulation **** C:/intelFPGA_lite/21.1/questa_fse/win64/vsim -c -do decoder2.do Error.Re: University VWF won't work
Hi Richard, I have the same issue, I have just installed the v21.1 Lite version and this is my first attempt at simulation. The transcript from the simulator is below, and my archive file is attached. Thank you in anticipation for your help. Tim Mulroy Determining the location of the ModelSim executable... Using: C:/intelFPGA_lite/21.1/questa_fse/win64 To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both Questa Intel FPGA Edition and ModelSim executables are available, Questa Intel FPGA Edition will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder2 -c decoder2 --vector_source="C:/Users/engtj/Quartus/decoder2/Waveform.vwf" --testbench_file="C:/Users/engtj/Quartus/decoder2/simulation/qsim/Waveform.vwf.vt" Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition Info: Copyright (C) 2022 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Jan 24 15:06:29 2023 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off decoder2 -c decoder2 --vector_source=C:/Users/engtj/Quartus/decoder2/Waveform.vwf --testbench_file=C:/Users/engtj/Quartus/decoder2/simulation/qsim/Waveform.vwf.vt Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Completed successfully. Completed successfully. **** Generating the timing simulation netlist **** quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="C:/Users/engtj/Quartus/decoder2/simulation/qsim/" decoder2 -c decoder2 Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition Info: Copyright (C) 2022 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Jan 24 15:06:30 2023 Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory=C:/Users/engtj/Quartus/decoder2/simulation/qsim/ decoder2 -c decoder2 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Warning (10905): Generated the EDA functional simulation netlist because it is the only supported netlist type for this device. Info (204019): Generated file decoder2.vo in folder "C:/Users/engtj/Quartus/decoder2/simulation/qsim//" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings Info: Peak virtual memory: 4657 megabytes Info: Processing ended: Tue Jan 24 15:06:30 2023 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:01 Completed successfully. **** Generating the ModelSim .do script **** C:/Users/engtj/Quartus/decoder2/simulation/qsim/decoder2.do generated. Completed successfully. **** Running the ModelSim simulation **** C:/intelFPGA_lite/21.1/questa_fse/win64/vsim -c -do decoder2.do Error.
