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UserID4331231's avatar
UserID4331231
Icon for Occasional Contributor rankOccasional Contributor
6 months ago

understanding Hex file creation

In my FPGA project I have couple of memory which I plan on using as Configuration memory and general purpose memory. In Platform designer I made my project and I intend to assign them some initial va...
Compilation
Hdl
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 months ago

No it means there's a mismatch between the RAM(s) you've created and the .hex files. How did you create the RAM? As IP or through HDL inference? What options did you choose?

UserID4331231's avatar
UserID4331231
Icon for Occasional Contributor rankOccasional Contributor
6 months ago
  1. In platform designer - in IP catalog - i chose "On chip memory II (RAM or ROM) IP". I entered S1 port width, and entered size of memory in decimal (1024 for 1K instance and 1048756 for 1M instance). I chose hex file i wanted to chose for initialization.
  2. Once entire project is made in platform designer I click on generate HDL , closed platform designer and synthesised project in quartus.

the Hex file was created with quartus gui

  1. I clicked on files - and in new file wizard chose "hexadecimal (intel-format) file".
  2. Gui asks for word size and number of words. I chose values as described above. I select cell - right click and chose "Custom Fill Cells". I chose options to get desired auto incrementing pattern.