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Altera_Forum's avatar
Altera_Forum
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9 years ago

Unconstrained output

First let me introduce my case， I simply used cyclone3 to communicate with a SSRAM, a 100MHZ clock coming into my FPGA ，which goes through a PLL and drives data out, the output of PLL is also 100MHZ.

I've followed steps of time quest user guide but still met a mistake, attached is my sdc file.

Reports remind me that my CLK port is unconstrained，but I‘ve already associate it to my PLL output clock，as a new designer of FPGA， I‘m puzzled about it，could anyone give me some suggests？

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Some Points:

    Either use create_generated_clock or derive_pll_clocks.

    Your create_clock command format is erroneous. The period should be 10.00 ns, not 10.00ns (Consider the space).

    Are you sure about your set_false_path command which cuts all the paths between the PLL input & output clock?

    For set_output_delay you can use ADDR

    [*], etc to be more comfort :):)

    What is your FPGA part & Quartus version?
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Sincerely thanks to your reply, I used quartus 13.1 and my FPGA part is EP3C25F324.

    With your guidance, I modified my design. And I met another question just as you mentioned.

    I‘m not quite sure about set false path between the two clocks, as I use sysclk to drive my FPGA and use the PLL output clock to control the communication between ssram.

    when I delete the set false path command， reports show that time requirements not met.

    slack is negative from node RST(input) to node ADDR and several registers.

    The launch clock is SYSCLK and the latch clock is the output clock of PLL.

    I think maybe I could use set_multicycle_path instead of set false path. As I need multiple clock cycles to perform operations to the RST signal.

    Am I right？ Sincerely thanks！
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    If you get negative slack on reset pin, you can resolve it using reset synchronizer and set_multicycle commands.

    If you are sure that no clock transfer occurs between your incoming clock & the PLL output you can set_false_path between domains.