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Altera_Forum
Honored Contributor
Honored ContributorUnconstrained output
First let me introduce my case， I simply used cyclone3 to communicate with a SSRAM, a 100MHZ clock coming into my FPGA ，which goes through a PLL and drives data out, the output of PLL i...
Altera_ForumHonored Contributor
Honored ContributorIf you get negative slack on reset pin, you can resolve it using reset synchronizer and set_multicycle commands.
If you are sure that no clock transfer occurs between your incoming clock & the PLL output you can set_false_path between domains.
