Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Unconstrained output

First let me introduce my case， I simply used cyclone3 to communicate with a SSRAM, a 100MHZ clock coming into my FPGA ，which goes through a PLL and drives data out, the output of PLL i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Sincerely thanks to your reply, I used quartus 13.1 and my FPGA part is EP3C25F324.

With your guidance, I modified my design. And I met another question just as you mentioned.

I‘m not quite sure about set false path between the two clocks, as I use sysclk to drive my FPGA and use the PLL output clock to control the communication between ssram.

when I delete the set false path command， reports show that time requirements not met.

slack is negative from node RST(input) to node ADDR and several registers.

The launch clock is SYSCLK and the latch clock is the output clock of PLL.

I think maybe I could use set_multicycle_path instead of set false path. As I need multiple clock cycles to perform operations to the RST signal.

Am I right？ Sincerely thanks！