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Altera_Forum's avatar
Altera_Forum
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9 years ago

Unconstrained output

First let me introduce my case， I simply used cyclone3 to communicate with a SSRAM, a 100MHZ clock coming into my FPGA ，which goes through a PLL and drives data out, the output of PLL i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Some Points:

Either use create_generated_clock or derive_pll_clocks.

Your create_clock command format is erroneous. The period should be 10.00 ns, not 10.00ns (Consider the space).

Are you sure about your set_false_path command which cuts all the paths between the PLL input & output clock?

For set_output_delay you can use ADDR

[*], etc to be more comfort :):)

What is your FPGA part & Quartus version?