Altera_Forum
Honored Contributor
Honored Contributorunconnect port warning.
when a instance port is not connected,
Quartus report a connectivty issue. how to avoid this.Forum Discussion
4 Replies
Altera_ForumIn VDHL use 'open'
E.g a : b port map ( clk => clk , ... thispin => open, ... ) ;- Altera_Forum
thank you. but i like use Verilog. Do you know how write Verilog code like this?
- Altera_Forum
Sorry, I wouldn't touch Verilog with a bargepole i.e. I don't know much about Verilog.
Let's hope the Verilog experts will step in. - Altera_Forum
In VHDL and verilog, any out ports left out are left open by default. But you must connect and input port to something if it has no default value, even if it's a constant.
WHy not post the actual error?
