Solved
Forum Discussion
KennyT_altera
Super Contributor
6 months agoDo you mean the DMA controller? If yes, if this guide is sufficient?
https://www.intel.com/content/www/us/en/docs/programmable/683130/25-1/dma-controller-core.html
Ashish_Pradhan
New Contributor
6 months agoHi Kenny Tan,
Thanks for your reply.
The DMA core is separate IP and hence these field descriptions does not suit.
"dma_read_master" (Read Master Intel FPGA IP) and "dma_write_master" (Write Master Intel FPGA IP) are two sub-core of modular Scatter Gather DMA. The user guide which is available for mSGDMA, and their field description seems not working for the above two mentioned IPs. So could you pls provide the document which the tool points to the link mentioned in the earlier post . I need to configure its "command_sink" channel.
Thanks & Regards,
Ashish.