Trouble simulating multiple verilog files

Question

Hi there!

I'm running ModelSim Altera Web Edition and having a bit of trouble simulating multiple Verilog files.

I have a 'top' module that uses and connects the modules of the other Verilog files. The simulation files is also generated from a Quartus II (also free edition) ... I have no problem simulating with just one Verilog/VHDL file.

Any restrictions that make this kind of trouble?

Thanks for your help!

altera_forum · Answer

there are no restrictions like that. in fact between a testbench and DUT there are already multiple Verilog files involved in the simulation.

altera_forum · Answer

Okey,  Any simple howto tutorials you can give me?  I have looked on this thread: http://www.alteraforum.com/forum/showthread.php?t=3707

altera_forum · Answer

I think I found a major flaw in my code ;)  Hah :p I will look on this first! # Update: 1. Didn't help :mad:

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Trouble simulating multiple verilog files

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