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Altera_Forum
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16 years ago

Trouble simulating multiple verilog files

Hi there! I'm running ModelSim Altera Web Edition and having a bit of trouble simulating multiple Verilog files. I have a 'top' module that uses and connects the modules of the other Veril...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

there are no restrictions like that. in fact between a testbench and DUT there are already multiple Verilog files involved in the simulation.