Trouble compiling my JK flip flop VHDL code!? "Syntax Error"

--The below code doesn't compile. I am given the following errors. Could someone help me troubleshoot this.

--ERRORS:

Error (10500): VHDL syntax error at lab4_jke.vhd(14) near text "if"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement

Error (10500): VHDL syntax error at lab4_jke.vhd(14) near text "then"; expecting "<="

Error (10500): VHDL syntax error at lab4_jke.vhd(15) near text "then"; expecting "<="

Error (10500): VHDL syntax error at lab4_jke.vhd(17) near text "elsif"; expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a concurrent statement

Error (10500): VHDL syntax error at lab4_jke.vhd(17) near text "then"; expecting "<="

Error (10500): VHDL syntax error at lab4_jke.vhd(19) near text "elsif"; expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a concurrent statement

Error (10500): VHDL syntax error at lab4_jke.vhd(19) near text "then"; expecting "<="

Error (10500): VHDL syntax error at lab4_jke.vhd(21) near text "elsif"; expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a concurrent statement

Error (10500): VHDL syntax error at lab4_jke.vhd(21) near text "then"; expecting "<="

Error (10500): VHDL syntax error at lab4_jke.vhd(23) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"

--CODE:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY lab4_jke IS

PORT(

S,R,J,K,CLK : IN STD_LOGIC;

Q : OUT STD_LOGIC;

NQ : OUT STD_LOGIC);

END lab4_jke;

ARCHITECTURE behavior OF lab4_jke IS

BEGIN

if (CLK'EVENT AND CLK='1') then

if (J='0' AND K='0') then

Q <= Q;

elsif (J='1' AND K='0') then

Q <= '1';

elsif (J='0' AND K='1') then

Q <= '0';

elsif (J='1' AND K='1') then

Q <= NOT(Q);

END if;

END if;

END behavior;