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Altera_Forum
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12 years ago

Trouble compiling my JK flip flop VHDL code!? "Syntax Error"

--The below code doesn't compile. I am given the following errors. Could someone help me troubleshoot this. --ERRORS: Error (10500): VHDL syntax error at lab4_jke.vhd(14) near text "if"; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

A JK flip-flop doesn't have Set and Reset inputs. may be you want a preset and clear asynchronous inputs. In a FPGA you do that with a single asynchronous reset:

process(clr, clk)

begin

if( clr = '1' ) then

q_reg <= '0';

elsif( clk'event and clk = '1' ) then

q_reg <= q_next;

end if;

end process;

q_next <= '0' when ( j = '0' and k = '1' ) else ....etc