Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Trouble compiling my JK flip flop VHDL code!? "Syntax Error"

--The below code doesn't compile. I am given the following errors. Could someone help me troubleshoot this. --ERRORS: Error (10500): VHDL syntax error at lab4_jke.vhd(14) near text "if"; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY lab4_jke IS

PORT(

S,R,J,K,CLK : IN STD_LOGIC;

Q : OUT STD_LOGIC;

NQ : OUT STD_LOGIC);

END lab4_jke;

ARCHITECTURE behavior OF lab4_jke IS

BEGIN

process(clk)

begin

if (CLK'EVENT AND CLK='1') then

if (J='0' AND K='0') then

Q <= Q;

elsif (J='1' AND K='0') then

Q <= '1';

elsif (J='0' AND K='1') then

Q <= '0';

elsif (J='1' AND K='1') then

Q <= NOT(Q);

END if;

END if;

end process;

END behavior;