transparent latch & dual edge flip-flops

Don't mix up between ASIC and FPGAs though both use similarly named tools but there is a lot of difference as well.

latches are common in ASICs but are avoided in FPGAs. FPGAs have only clked registers and no special small size dedicated latches (without clk). consequently they suffer more delay in case of fpgas. a latch is a case of combinatorial feedback.Timing analysis tools can't do well with latches and combinatorial feedbacks in FPGas.

two edge flip ?? can't get through the link. I don't think vendors are keen on more than one edge triggering due to design tradition and speed problems. After all they can get you tons of registers.

ASIC designers also don't care about gated clk as much as fpga do. The reason is routing in fpga is though a prefabricated spaghetti...

OK, ASIC might be different although the theoretical discussion seems not dependant on the target. Still, is there something to think about when mixing schematics and VHDL in Quartus so that the schematics does not get optimized in the final design? For instance, if the top entity is VHDL, maybe Quartus makes VHDL of any schematics files and optimizes them too? Any settings in Quartus to allow/avoid this?

Here is the link to dual-edge flip-flop: (start with http://)

asicdigitaldesign.wordpress.com/2008/09/22/another-look-at-the-dual-edge-flip-flop/

schematic or HDL ...etc are all design entry files that are pocessed down to a netlist by synthesis tool(e.g. to edif description) then mapped by fitter tool to target technology(LUTs ..etc). In FPGAs the logic is not implemented in traditional gates at all but in LUTs + registers.

Hence what you see in a schematic is not what you are going to get anyway and must be mapped down to LUTs. Preventing compiler optimisation is threfore vague. You can logiclock certain areas(or generate vqm netlist...) or you can use "keep" attributes.

Apart from occasional cases, I don't see any reason to stop compiler optimisation unless you don't trust it.

Make sure that what you are trying to do is actually supported by the underlying architecture of the part by reading the core architecture details in the handbook of the FPGA. For example, I'm not sure there are any Altera parts that have dual-edge flip-flops. Xilinx has them in the CoolRunner2 series, but that's the only FPGA I'm aware of that has them (and it's actually a CPLD, not an FPGA).

Latches have somewhat more presence in modern FPGAs, but there's still a chance whatever family you're using doesn't support them. Again, read the core architecture section of your FPGA's handbook; it will tell you *exactly* what is contained in the LE/ALM. For example, the Cyclone III handbook's section on the LE registers says, "You can configure the programmable register of each LE for D, T, JK, or SR flipflop operation."

All that aside, actual transparent latches are generally not a good thing to try in an FPGA. See if you can't rethink your design to be more synchronous; your timing analyzer will thank you. :-)

There are always some places in FPGA design, where latches are needed. They are basically working. But you should consider their limitation and avoid them, if you can.

Regarding dual edge flip-flops: Only a few CPLD families have it truely in hardware (no Altera device). With most FPGA and CPLD families, you must use one of the said surrogates made from two flip-flops and combinational glue logic. You have to check if their timing is suitable for your design. I think, it can be meaningful in few special cases.