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Altera_Forum's avatar
Altera_Forum
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16 years ago

transparent latch & dual edge flip-flops

I read that a transparent latch is tricky to ensure in VHDL code. In principle, one must include a redundant term that the compiler might take away. http://www.velocityreviews.com/forums/t57539-la...
Altera_Forum's avatar
Altera_Forum
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16 years ago

OK, ASIC might be different although the theoretical discussion seems not dependant on the target. Still, is there something to think about when mixing schematics and VHDL in Quartus so that the schematics does not get optimized in the final design? For instance, if the top entity is VHDL, maybe Quartus makes VHDL of any schematics files and optimizes them too? Any settings in Quartus to allow/avoid this?

Here is the link to dual-edge flip-flop: (start with http://)

asicdigitaldesign.wordpress.com/2008/09/22/another-look-at-the-dual-edge-flip-flop/