transparent latch & dual edge flip-flops

schematic or HDL ...etc are all design entry files that are pocessed down to a netlist by synthesis tool(e.g. to edif description) then mapped by fitter tool to target technology(LUTs ..etc). In FPGAs the logic is not implemented in traditional gates at all but in LUTs + registers.

Hence what you see in a schematic is not what you are going to get anyway and must be mapped down to LUTs. Preventing compiler optimisation is threfore vague. You can logiclock certain areas(or generate vqm netlist...) or you can use "keep" attributes.

Apart from occasional cases, I don't see any reason to stop compiler optimisation unless you don't trust it.