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Altera_Forum
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16 years ago

transparent latch & dual edge flip-flops

I read that a transparent latch is tricky to ensure in VHDL code. In principle, one must include a redundant term that the compiler might take away. http://www.velocityreviews.com/forums/t57539-la...
Altera_Forum's avatar
Altera_Forum
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16 years ago

There are always some places in FPGA design, where latches are needed. They are basically working. But you should consider their limitation and avoid them, if you can.

Regarding dual edge flip-flops: Only a few CPLD families have it truely in hardware (no Altera device). With most FPGA and CPLD families, you must use one of the said surrogates made from two flip-flops and combinational glue logic. You have to check if their timing is suitable for your design. I think, it can be meaningful in few special cases.