transparent latch & dual edge flip-flops

Don't mix up between ASIC and FPGAs though both use similarly named tools but there is a lot of difference as well.

latches are common in ASICs but are avoided in FPGAs. FPGAs have only clked registers and no special small size dedicated latches (without clk). consequently they suffer more delay in case of fpgas. a latch is a case of combinatorial feedback.Timing analysis tools can't do well with latches and combinatorial feedbacks in FPGas.

two edge flip ?? can't get through the link. I don't think vendors are keen on more than one edge triggering due to design tradition and speed problems. After all they can get you tons of registers.

ASIC designers also don't care about gated clk as much as fpga do. The reason is routing in fpga is though a prefabricated spaghetti...