transparent latch & dual edge flip-flops

Make sure that what you are trying to do is actually supported by the underlying architecture of the part by reading the core architecture details in the handbook of the FPGA. For example, I'm not sure there are any Altera parts that have dual-edge flip-flops. Xilinx has them in the CoolRunner2 series, but that's the only FPGA I'm aware of that has them (and it's actually a CPLD, not an FPGA).

Latches have somewhat more presence in modern FPGAs, but there's still a chance whatever family you're using doesn't support them. Again, read the core architecture section of your FPGA's handbook; it will tell you *exactly* what is contained in the LE/ALM. For example, the Cyclone III handbook's section on the LE registers says, "You can configure the programmable register of each LE for D, T, JK, or SR flipflop operation."

All that aside, actual transparent latches are generally not a good thing to try in an FPGA. See if you can't rethink your design to be more synchronous; your timing analyzer will thank you. :-)