Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Timing violations with a reset signal

I created a global reset signal, which is active low.

Generating reset signal codes are from Reset_Delay.v as an example from Altera site.

(https://cloud.altera.com/devstore/platform/16.0.0/standard/usb-sd-card-mass-storage-design/)

For this module, I uses slowest clock(100Mhz) from a PLL.

But due to more faster clocks(2 shifted phase 250Mhz), I got some timing violations with that reset signals.

How can I remove these timing violations related to that reset signal?

Adding SDC? if yes, how to? or any other methods?

I use MAX10 device.

Please, help me.

Thanks

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Hi,

    You will have to add the reset signal as a False path in the SDC file for the project. Add a new file to the project and select Timing constraints SDC. Once the SDC file is added, you can right-click anywhere in the empty file and choose the Templates option. From here select the timing related and under this expand the false paths constraints. Once you double-click it, a false path constraint will be added to the SDC. Edit it with the correct reset and clock signal names, save and re-run the synthesis. This should clear up the reset timing violations.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    --- Quote Start ---

    Hi,

    You will have to add the reset signal as a False path in the SDC file for the project. Add a new file to the project and select Timing constraints SDC. Once the SDC file is added, you can right-click anywhere in the empty file and choose the Templates option. From here select the timing related and under this expand the false paths constraints. Once you double-click it, a false path constraint will be added to the SDC. Edit it with the correct reset and clock signal names, save and re-run the synthesis. This should clear up the reset timing violations.

    --- Quote End ---

    Setting false path is only possible if that path is indeed false otherwise you get a false timing pass.

    For reset to be false it requires that nothing is done when reset is deasserted at least for several clocks and then you can just set that path as multicycle.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    The straightforward way is to implement a reset synchronizer for each clock, it will also abandon the timing violations.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    I see.

    Thanks you guys,

    Let me try what you guys mentioned.

    Regards,