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Altera_Forum's avatar
Altera_Forum
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8 years ago

Timing violations with a reset signal

I created a global reset signal, which is active low. Generating reset signal codes are from Reset_Delay.v as an example from Altera site. (https://cloud.altera.com/devstore/platform/16.0.0/stan...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

The straightforward way is to implement a reset synchronizer for each clock, it will also abandon the timing violations.