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Hi,
You will have to add the reset signal as a False path in the SDC file for the project. Add a new file to the project and select Timing constraints SDC. Once the SDC file is added, you can right-click anywhere in the empty file and choose the Templates option. From here select the timing related and under this expand the false paths constraints. Once you double-click it, a false path constraint will be added to the SDC. Edit it with the correct reset and clock signal names, save and re-run the synthesis. This should clear up the reset timing violations.
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Setting false path is only possible if that path is indeed false otherwise you get a false timing pass.
For reset to be false it requires that nothing is done when reset is deasserted at least for several clocks and then you can just set that path as multicycle.
Honored Contributor
