Timing violations with a reset signal

Hi,

You will have to add the reset signal as a False path in the SDC file for the project. Add a new file to the project and select Timing constraints SDC. Once the SDC file is added, you can right-click anywhere in the empty file and choose the Templates option. From here select the timing related and under this expand the false paths constraints. Once you double-click it, a false path constraint will be added to the SDC. Edit it with the correct reset and clock signal names, save and re-run the synthesis. This should clear up the reset timing violations.