Forum Discussion
Occasional ContributorTiming Violations in JTAG Signals
After internal testing and discussion, we’ve confirmed the following for Arria 10 devices:
- Only the on-board USB-Blaster II is capable of supporting up to 24 MHz.
- The off-board USB-Blaster II cannot reach 24 MHz due to certain limitations
- That said, if the TDO pin of the Arria 10 is driving the TDI of another device through a short trace, it can still support up to 24 MHz.
In the SDC files, you’ll notice a placeholder such as <<customer here>>. This needs to be updated based on the actual trace length measurements on your board. If you're targeting 24 MHz, the timing constraints will need to be tighter to meet the higher frequency requirements.
I'll attach a sample SDC file that helps close timing at higher speeds. Let me know if you have any further questions.
Super ContributorAfter running several tests on a smaller design, we observed that violations may occur if Signal Tap has been previously enabled. Once enabled, Quartus tends to retain the configuration and automatically adds an additional module named auto_fab_0. The issue appears to be linked to the encrypted Signal Tap IP.
To address this, please ensure that all constraints are properly defined for your board. You may need to customize the constraint settings accordingly. For reference, Intel provides detailed guidance on JTAG constraints here:
If all constraints are correctly applied and aligned with your board configuration, we recommend reducing the operating frequency to 16 MHz as a next step.
Additionally, I will further investigate whether this issue is related to a potential bug in the current version of Quartus by comparing it with older releases. I’ll follow up with more findings soon. Thanks
