Forum Discussion
Occasional ContributorTiming Violations in JTAG Signals
After internal testing and discussion, we’ve confirmed the following for Arria 10 devices:
- Only the on-board USB-Blaster II is capable of supporting up to 24 MHz.
- The off-board USB-Blaster II cannot reach 24 MHz due to certain limitations
- That said, if the TDO pin of the Arria 10 is driving the TDI of another device through a short trace, it can still support up to 24 MHz.
In the SDC files, you’ll notice a placeholder such as <<customer here>>. This needs to be updated based on the actual trace length measurements on your board. If you're targeting 24 MHz, the timing constraints will need to be tighter to meet the higher frequency requirements.
I'll attach a sample SDC file that helps close timing at higher speeds. Let me know if you have any further questions.
Occasional ContributorThe sdc file is active in the project and also in the timing Analyzer settings.
I am sorry, I cannot share my complete project, as it contains Intellectual Property of the company.
The failing paths are explicitly not covered by the .sdc constraint from the Intel Manual:
# Cut a few timing paths that are not related to JTAG logic in # the FPGA core, such as security mode. set_false_path -from [get_ports {altera_reserved_tdi}] -to [get_ports {altera_reserved_tdo}] if { [get_collection_size [get_registers -nowarn *~jtag_reg]] > 0 } { set_false_path -from [get_registers *~jtag_reg] -to [get_ports {altera_reserved_tdo}] }
The violations are about the tdo_reg
-18.207 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_8 altera_reserved_tdo altera_reserved_tck (INVERTED) altera_reserved_tck (INVERTED) 33.333 -2.582 4.240 Slow 950mV 100C Model
The Question is, is this intentional? and how to debug timing issues within an encrypted core?
Or are the tdo_reg constraints missing in the sdc file?
Thanks
Fabian
