Timing violation with Altera GPIO in DDR mode

I have a setup violation at the register after the input register. The input register is constrained as described in AN433.

set_input_delay -add_delay -clock virt_adc_clk -min -0.6             [get_ports {ADC_DATA[*]}] 
set_input_delay -add_delay -clock virt_adc_clk -min -0.6 -clock_fall [get_ports {ADC_DATA[*]}] 
 
set_input_delay -add_delay -clock virt_adc_clk -max  0.6             [get_ports {ADC_DATA[*]}]
set_input_delay -add_delay -clock virt_adc_clk -max  0.6 -clock_fall [get_ports {ADC_DATA[*]}]
 
set_false_path -setup -fall_from [get_clocks virt_adc_clk] -rise_to \
[get_clocks CLK262]
set_false_path -setup -rise_from [get_clocks virt_adc_clk] -fall_to \
[get_clocks CLK262]
set_false_path -hold -rise_from [get_clocks virt_adc_clk] -rise_to \
[get_clocks CLK262]
set_false_path -hold -fall_from [get_clocks virt_adc_clk] -fall_to \
[get_clocks CLK262]

But now i have the violation after the input register, as you can see in the picture from Timequest.

Do I miss something?