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MRenn's avatar
MRenn
Icon for New Contributor rankNew Contributor
6 years ago

Timing violation with Altera GPIO in DDR mode

I have a setup violation at the register after the input register. The input register is constrained as described in AN433. set_input_delay -add_delay -clock virt_adc_clk -min -0.6 [get...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

Logic lock helps in timing but not all the time; it actually depends on the design. I have been working on this for some time and tried different methods to close the timing. Unfortunately, the best result I can get is -0.297ns violation on Slow 900mV -40C Model. Also, I have checked with the team, the suggestion is to use Phylite instead of GPIO for frequency higher than 200MHz. Please use Phylite as this is also suggested in our documentation.

Thanks.