timing simulation in modelsim after quartus place and route

Hi,

I wrote a simple RAM in deffernt versions.

I get data and address and my output is the address and the data

after place and route and running timing simulation (checked at least 10 different versions)

I never get my signals synchronized to the clk (rising_edge)

for example:

entity sobel_ram_start_double_process is

generic(add_width: integer:= 2;data_width: integer:= 4);

port ( clk : in std_logic;

wr_en : in std_logic;

data_in : in std_logic_vector (data_width-1 downto 0);

address : in std_logic_vector (add_width-1 downto 0);

address_ram1 : out std_logic_vector (add_width-1 downto 0);

data_out : out std_logic_vector (data_width-1 downto 0));

end entity;

architecture sobel_ram_start_double_process_arch of sobel_ram_start_double_process is

type mem is array (2**add_width-1 downto 0) of std_logic_vector(data_width-1 downto 0);

signal array_data : mem;

signal address_save : std_logic_vector(add_width-1 downto 0);

begin

getting_data:process(clk)

begin

if rising_edge(clk) then

if wr_en='1' then

array_data(conv_integer(address))<=data_in;

end if;

end if;

end process;

address_saving:process(clk)

begin

if rising_edge(clk) then

if wr_en='1' then

address_save<=address;

address_ram1<=address_save;

end if;

end if;

end process;

end architecture;

In modelsim it works perfect but after using *.vho and *.sdo

I dont understand what the quartus does!!!

address_ram1 gets a value without my initialization...

instead of simple pipeline implementation the data is presented in strange way...

I tried almost every version (2 process, 1 process, outside the process)

and couldn't synchronize my signals (address_ram1 and the output) the the clk :-(

even under the same wr_en I get the data with delay (and not the delta)...

What should I do?

Tenx

ari