timing simulation in modelsim after quartus place and route

I think you are simulating with modelsim at RTL level. i.e. with no routing delays eveything switches in zero time. All signals change on clock edges.

If you are using the vho file in the Quartus simulator then this is a gate level netlist and includes all the timings post synthesis (Actually the timing info is also in the sdo). If you like this is real timings with real delays through RAMS etc.

Hence RAM output signals etc will be delayed until after the clock edge. This is your RAM latency.

Hope this helps