timing simulation in modelsim after quartus place and route

Ari

I can't see where your code assigns data_out, so i can't advise on why it's not synchronised.

When the real logic and routing delays are included in your simulation, you will see signals changing a short time after the clock edge (essentially you can regard your RTL simulation as having the logic and routing delays reduced to zero). Is that all that you are seeing or are your outputs completely unsynchronised?

Mouna

It looks like you don't have all of the libraries that you need. Look in the library list and check that the necessary Altera libraries are there - if not add them in.