timing simulation in modelsim after quartus place and route

hello,

I want to run an EDA gate level simulation to my VHDL design using QuartusII 6.1 and Altera Modelsim 6.1g but when i run the simulation I obtain this error:

** warning: (vsim-3473) component instance "soc : mapping_minimips" is not bound.

# time: 0 ps iteration: 0 region: /test_mm file: d:/these/inria/fpga_2s180/vga/4pe_avecvga/avec_xnet_and_linear/test_mm.vhd

# ** fatal: sdf files require altera primitive library

# time: 0 ps iteration: 0 instance: /test_mm file: d:/these/inria/fpga_2s180/vga/4pe_avecvga/avec_xnet_and_linear/test_mm.vhd line: unknown

# fatal error while loading design

# error loading design

# error: error loading design

# pausing macro execution

# macro ./standard_run_msim_gate_vhdl.do paused at line 12

Could you please help me,

thanks in advance

Mouna.