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johnt2's avatar
johnt2
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1 year ago

timing setup failure when using altera_lvds_core20_iopll.

Hello,

I am receiving several setup errors when using the altera LVDS deserializer IP in the IOPLL.

afe_rx1|u0|lvds_0|core|arch_inst|internal_pll.pll_inst|altera_lvds_core20_iopll|outclk[6]

OUTCLK[6], OUTCLK[5] and OUTCLK[2]

I saw a post discussong the IP order in assignment editor, but this did not resolve the issue.

These are all signals internal to the IP, so I don't know how to address the issue.

Thanks,

John

Timing

2 Replies

  • TingJiangT_Intel's avatar
    TingJiangT_Intel
    Icon for Contributor rankContributor
    1 year ago

    Could you show the detail path in Timing analyzer and share the solution you tried.

    Thanks


  • TingJiangT_Intel's avatar
    TingJiangT_Intel
    Icon for Contributor rankContributor
    1 year ago

    As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.