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New Contributor

2 years ago

timing setup failure when using altera_lvds_core20_iopll.

Hello, I am receiving several setup errors when using the altera LVDS deserializer IP in the IOPLL. afe_rx1|u0|lvds_0|core|arch_inst|internal_pll.pll_inst|altera_lvds_core20_iopll|outclk[6] OUTCLK...

TingJiangT_Intel

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Contributor

2 years ago

Could you show the detail path in Timing analyzer and share the solution you tried.

Thanks