Timing Constraints.

Hi sir/madam.

I'm working on MAX10 FPGA to interface USB 2.0 with FPGA to send image data pixels to PC . Problem is my verilog design is not able achieve timing constraints (designed for 60 MHz clock and achieved to 58 MHz ) i saw this in timing analyzer in quartus software. Can i get help on how to design FPGA projects to meet timing constarints. I'm new to FPGA design technology.

Thanks in advance.