Forum Discussion
m_kumar
Occasional Contributor
Occasional ContributorTiming Constraints.
Hi sir/madam.
I'm working on MAX10 FPGA to interface USB 2.0 with FPGA to send image data pixels to PC . Problem is my verilog design is not able achieve timing constraints (designed for 60 MHz cl...
SchroetiOccasional Contributor
Occasional ContributorIn Quartus you can use the Timing Optimization Advisor from menu:
Tools/Advisors/Timing Optimization Advisor
to get some good advice.
m_kumarThanks for the reply sir. Also can i get any design tips for fpga design.
sstrellSuper Contributor
There's lots of training available for timing analysis. Start here:
- m_kumar
Thank you sir.
- Schroeti
This document gives advice on many things concerning timing:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an584.pdfAlso some design tips are listed.
- m_kumar
Thank sir
