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maitreya_ranade
New Contributor
New ContributorTiming analysis for Asynchronous part of design
We have a product comprising of multiple FPGAs talking to eachother via MLVDS lines based on bandwidth allocation. The data is shared across on 100MHz MLVDS lines and is asynchronous in nature. The c...
Hi,
If those are asynchronous, you may set false path to the asynchronous input and output check this link https://www.intel.com/content/www/us/en/docs/programmable/683062/17-1/setting-timing-constraints-using-the.html
maitreya_ranadeNew Contributor
New ContributorThank you @ShengN_Intel for resolving this issue. I have marked this as resolved!
