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Altera_Forum's avatar
Altera_Forum
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14 years ago

TimeQuest

I have a PLL with its input clock from a port (physical pin) as shown as attached. This clock is specified as a base clock. Then "derive_pll_clocks" is added. The following constraint is also added.

create_generated_clock -name {ext_dac_clk} -source inst12|altpll_component|pll|clk[2] -offset 0.500 [get_ports {ext_dac_clk}]

However, the TimeQuest creates a message.

From "inst12|altpll_component|pll|clk[2]" to "ext_dac_clk" from Clocks "dac_clk_in" is "Unconstrained Output Port Paths"

I don't know why. Please help to explain. Many thanks.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    It's annoying. TQ says that, as there is no set_output_delay constraints on it. My opinion is that there doesn't need to be. Usually you're constraining other outputs in relation to this clock, so if that meets timing all is fine. It would be like saying input port dac_clk_in is unconstrained because it doesn't have a set_input_delay constraint on it.

    I've been trying to get that changed, but no luck.

    There are some ways to get around it, but they're a bit ugly and I generally don't think worth it. I prefer accepting that TQ says this.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I agree with Rysc. However, if you don't want to see the unconstrained path, you can create a false_path constraint to the clock output port.