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Honored ContributorTimeQuest Timing Analyzer[Setup slack analysis]
HI,
I am trying to understand how the Time Quest analyzer calculating required setup and hold time.I have written code for register and the clocks are common(50 MHz). As per my understanding data required time for setup calculation = clock arrival time -Tsu - Setup Uncertainty. From the Time Quest analyzer clock arrival time = 22.982ns[ from source latency to clock pessimism] Tsu = 0.021ns Setup Uncertainty = 0ns data required time = 22.982 - 0.021 = 22.961ns. But the tool showing the calculation like below mentioned way, data required time = 22.982 + 0.021 = 23.003ns.? If i am not wrong the data required time should be 22.961ns.Please let me whether my understanding is correct or not? For your ref ------------------------------------------------------------------------------------------------------------------------ path summry:from node q1_s
to node q~reg0
launch clock clk
latch clock clk
data arrival time 3.945
data required time 23.003
slack 19.058 ------------------------------------------------------------------------------------------------------------------------ data required path:
total incr rf type fan out location element
20.000 0.000 source latency
20.000 0.000 1 pin_31 clk clk
20.000 0.000 rr ic 1 ioibuf_x0_y14_n1 clk~input|i
20.990 0.990 rr cell 1 ioibuf_x0_y14_n1 clk~input|o
21.182 0.192 rr ic 1 clkctrl_g4 clk~inputclkctrl|inclk[0]
21.182 0.000 rr cell 2 clkctrl_g4 clk~inputclkctrl|outclk
22.339 1.157 rr ic 1 ff_x1_y10_n17 q~reg0|clk
22.957 0.618 rr cell 1 ff_x1_y10_n17 q~reg0
22.982 0.025 clock pessimism
23.003 0.021 utsu 1 ff_x1_y10_n17 q~reg0
--------------------------------------------------------------------------------------------------------------------------------
Thanks in advance, Karthi.S
31 Replies
Altera_Forum--- Quote Start --- I'm not sure we're talking about the same thing.. What I'm saying is that, at the lowest level you have a circuit you can call a flip-flop, you can have negative Tsu or negative Th. In Altera terms, that's having a negative uTsu or a negative uTh. And not only you can have, but having negative Th is the prevalent type of flip-flop in integrated circuits nowadays. So, there's no sense in a convention that (u)Tsu and (u)Th are always positive. That convention falls apart in the face of actual, existing, circuits. --- Quote End --- The central theme in register timing is that a register(at its port level) needs input not to change before its clock edge (by +tSU time) and not to change after clock edge (by +tH time). So they must be positive. They only get negative relative to clock edge if you move your definition forwards say to clock/data pins.- Altera_Forum
No, you really can design flip-flop circuits (registers) where that is not true! :)
Ie, this cell library has a FF with a Tsu of 180 ps and Th of -95 ns. And the definition point are the terminals of the FF circuit. This means the signal on the D input terminal must stay stable from 180 ps BEFORE the rising edge of the signal on the CLK input terminal and until 95 ps BEFORE the rising edge of the signal in the CLK input terminal. If D changes 50 ps before the CLK rising edge.. it's OK! - Altera_Forum--- Quote Start --- No, you really can design flip-flop circuits (registers) where that is not true! :) Ie, this cell library has a FF with a Tsu of 180 ps and Th of -95 ns. And the definition point are the terminals of the FF circuit. This means the signal on the D input terminal must stay stable from 180 ps BEFORE the rising edge of the signal on the CLK input terminal and until 95 ps BEFORE the rising edge of the signal in the CLK input terminal. If D changes 50 ps before the CLK rising edge.. it's OK! --- Quote End --- I am talking specifically about fpga D flops. Ofcourse one can design a flop with internal delays to change timing to negative but that is totally irrelevant on this forum.
- Altera_Forum
I see no reason why FPGA FFs are different in this regard of FFs for standand cell and full custom ICs.
- Altera_Forum
The flop is a two state sampling device. By law of nature a sampling device needs to recognise its input state during a finite sampling window. If the input state is neither low nor high for a finite time then sampling naturally fails. That is the whole point. The second issue is how to measure this sampling window relative to what.
FPGAs view it at lowest level at flop ports before any further delays are inserted. It is possible that some fpgas may be produced with its internal intrinsic delays and hence the reference point changes. But the central physical theme stays regarding sampling a stable input. - Altera_Forum
Just let me make this clear.
These FF with negative Th do NOT have extra delay buffers for the purpose of having negative Th. These FFs are highly optimized circuits, for area/power/speed and the negative Th is a side-effect of the circuit design and the balance of the various paths inside the circuit. - Altera_Forum--- Quote Start --- Just let me make this clear. These FF with negative Th do NOT have extra delay buffers for the purpose of having negative Th. These FFs are highly optimized circuits, for area/power/speed and the negative Th is a side-effect of the circuit design and the balance of the various paths inside the circuit. --- Quote End --- going back to original thread. if micro tSU is negative then the report should say that.If it is positive it should say that. It clearly states a positive value on micro tSU in first post. So the question is again why the required data time equation says subtract tSU but the tool is adding it???
- Altera_Forum
That I can only speculate.
My impression is that, in general, FPGA tools work with a "gate level" representation of the circuit which mashes up the physical delay into abstractions. And as a result, they end up doing/having to do weird things. I have to admit I have considerably more difficulty following TQs path information than I have with IC tools. I was only taking issue with the concept that Tsu/Th are always negative by convention. - Altera_Forum
I have recently been involved with xilinx vivado that is replacing ISE and specifically it is xilinx attempt to catch up with timequest. They follow the same standards of synopsis sdc. Their documentation frankly is much better, shorter and up to the point with no excesses.
Timequest gives a lot of information, equations that are not relevant at field. In fact I don't want to know how they internally calculate slack but I need to know basics of managing negative slack. There are several equations for computing slack but that is for the tooland I don't need to know that but discrepancies are really painful and the more one reads timequest the more pain one gets! - Altera_Forum
Hmm, that said... I'm not sure TQ was saying uTsu was positive in one place and negative in another place.
The OP made it look like that but... the only place where I see Tsu in TQ is in the "data required report". All the values there are, by convention, positive when they increase the "Data required" timing. I.e., positive uTsu show up as negative increments and negative uTsu as positive increments. I haven't bothered to fire up Vivado yet, as none of my current projects is going with a 7 series. Xilinx's doc has always been pretty good. Their software on the other hand, has induced several fits of homicidal rage. I do hope Vivado improves things.
