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Altera_Forum
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12 years ago

TimeQuest Timing Analyzer[Setup slack analysis]

HI, I am trying to understand how the Time Quest analyzer calculating required setup and hold time.I have written code for register and the clocks are common(50 MHz). As per my understanding da...
Altera_Forum's avatar
Altera_Forum
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12 years ago

That I can only speculate.

My impression is that, in general, FPGA tools work with a "gate level" representation of the circuit which mashes up the physical delay into abstractions.

And as a result, they end up doing/having to do weird things.

I have to admit I have considerably more difficulty following TQs path information than I have with IC tools.

I was only taking issue with the concept that Tsu/Th are always negative by convention.