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No, you really can design flip-flop circuits (registers) where that is not true! :)
Ie, this cell library has a FF with a Tsu of 180 ps and Th of -95 ns. And the definition point are the terminals of the FF circuit.
This means the signal on the D input terminal must stay stable from 180 ps BEFORE the rising edge of the signal on the CLK input terminal and until 95 ps BEFORE the rising edge of the signal in the CLK input terminal.
If D changes 50 ps before the CLK rising edge.. it's OK!
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I am talking specifically about fpga D flops.
Ofcourse one can design a flop with internal delays to change timing to negative but that is totally irrelevant on this forum.
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